1. Field of the Invention
The invention relates to computer buses, and more specifically, to a method and apparatus for tracking bus transactions.
2. Description of Related Art
FIG. 1 illustrates a portion of a typical prior art computer system, such as a personal computer (PC), including one or more processors 10 and a chipset 12 coupled together by means of a processor bus 14. The chipset 12 is coupled to a memory device 15 such as a dynamic random access memory (DRAM) device and an input/output (I/O) bus 16.
A bus is like a highway on which data travel within a computer. It is simply a channel over which information flows between two or more devices. A bus normally has access points, or places into which a device can tap to become attached to the bus, and devices on the bus can send to, and receive information from, other devices. The processor bus 14 is the bus that the chipset 12 and the processors 10 use to communicate with each other. Computer systems also typically include at least one I/O bus 16, such as a peripheral component interconnect (PCI) bus, which is generally used for connecting performance-critical peripherals to the memory 15, chipset 12, and processor 10. For example, video cards, disk storage devices, high-speed network interfaces generally use a bus of this sort. PCs typically also include additional I/O buses, such as an industry standard architecture (ISA) bus, for slower peripherals such as mice, modems, regular sound cards, low-speed networking, and also for compatibility with older devices.
Each transaction initiated on the processor bus 14 goes through three general stages: the arbitration phase, the address phase, and the data phase. For a component, or agent, connected to the bus 14 to initiate a transaction on the bus 14, the agent must obtain "ownership" of the bus 14. This happens during the arbitration phase, where the agent initiating the transaction, known as the requesting agent, signals that it wants to use the bus 14. Once the requesting agent acquires bus ownership, it sends an address out on the bus 14 during the address phase that identifies the target of the transaction --the target agent. The other agents on the bus 14 receive the address and determine which of them is the target agent. Finally, during the data phase, the requesting agent waits for the target agent to provide the requested read data or to accept the write data.
These general stages of a bus transaction may be further divided into additional phases on more complex buses. These phases, for example, may include the following: arbitration phase, request phase, error phase, snoop phase, response phase, and data phase. The bus may be divided into groups of signals that generally correspond to the transaction phases, each of which is only used during the respective phase of a transaction.
Further, the bus may be designed to allow various phases of several different bus transactions to occur simultaneously to improve bus performance. This is known as "pipelining." When a request agent finishes with the request phase signal group for a specific transaction, it relinquishes control of that signal group and takes ownership of the signal group for the next phase. For example, once the request agent has issued its transaction request and is ready to check the error phase signals, it no longer requires the use of the request phase signals. It relinquishes control of the request phase signals and allows another transaction to be initiated. Thus, one transaction may be in the error phase while another transaction is simultaneously in the request phase.
Specific bus transactions, such as data reads or writes, may take a relatively long time to complete, or the target agent may be busy, and therefore, not available to immediately complete the request. In cases such as these, the target agent may choose to defer responding to the transaction request to a later time, in which case the target agent is called a deferring agent. Further, the target agent may assert a retry signal, notifying the requesting agent that the target agent cannot handle the transaction now, and the requesting agent should try the transaction again later.
The requesting agent keeps track of each transaction it initiates. Typically, the requesting agent records transaction information, such as the target agent's address, transaction type, transaction phase, etc., in a buffer. A typical transaction proceeds through the various phases and completes, then the transaction information is removed from the buffer, making room for additional transactions.
If a transaction is deferred, the transaction information is kept in the buffer until the transaction completes. For example, in a memory read transaction issued by a processor 10, the processor 10 may provide an identification of the request type and the memory address from which to read the data during the request phase. If the target agent (the memory controller of the chipset 12) cannot handle the request immediately, or if the transaction will take a relatively long time to complete, it may defer the request. The chipset 12 may complete the memory read at a later time, and then initiate another transaction to provide the data to the processor 10. The information regarding the original memory read transaction must be stored in the buffer until the chipset 12 provides the data in the subsequent bus transaction, so that the processor can determine with which transaction the received data is associated.
Processor performance typically has outpaced memory performance, increasing the latency in memory accesses and resulting in more deferred transactions. The buffer space for storing deferred transaction information is limited. If the buffer fills up, the processor 10 stalls, waiting for deferred transactions to complete before additional transactions may be initiated. One attempt to reduce the effect of this latency is to increase the buffer size such that additional deferred bus transactions may be tracked. The increased buffer size, however, has the undesirable effect of increasing the physical size of the processor package, and in turn, increasing the cost of the processor.
The present invention addresses the above discussed, and other, shortcomings of the prior art.